1. Field of the Invention
The present invention relates to a so-called scan path testing, and more specifically, to a logic integrated circuit for the scan path system.
2. Description of related art
As one means for ensuring testability of digital networks, the scan path system has been proposed, as reviewed in IEEE TRANSACTIONS ON COMPUTERS, Vol C-31, No. 1, January 1982, pp 7-11. In the conventional logic integrated for this scan path system, there have been provided terminals dedicated for only the scan path test, which include a clock signal terminal for a shift register, an input signal terminal for the shift register, an output signal terminal for the shift register, and a terminal for a scan control signal for selection between a normal mode and a shift register mode in the scan path testing. On the other hand, a recent advancement has increased the length of data processed in an integrated circuit. This inclination will require decrease of the number of terminals other than data terminals, because the integrated circuit can have only a limited number of terminals.